1. Field of Invention
The field of the present invention relates in general to phase-locked loop circuitry and in particular to a charge pump suitable for use in phase-locked loops.
2. Description of the Related Art
A phase locked loop (PLL) is a closed loop feedback system that in its simplest form, generates an error signal proportional to the phase difference between a fixed reference signal and the oscillations output by a voltage controlled oscillator (VCO) and which use the error signal to drive the VCO in a direction which reduces the phase errors. In its most basic implementation a PLL includes: a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), and a Voltage/Current controlled oscillator VCO. The PFD accepts input from the fixed reference signal and feedback of the variable signal output by the VCO, and provides the error signal as an output. The PFD error signal, either common mode or differential, is used to drive the charge pump. The charge pump operates as a bipolar current source converting the error signal from the PFD into positive and negative current pulses which are attenuated by the LPF before driving the VCO in a direction which reduces any measured phase error between the reference and feedback signal.
In a typical application a PLL is used to synthesize a high frequency VCO output signal from a lower frequency fixed reference signal. Clock synthesizers, switching regulators and Radio Frequency (RF) transceivers incorporate PLLs with this capability. Where the high desired high frequency VCO output signal is a fixed integer multiple of the fixed reference signal, the PLL will include a fixed integer frequency divider in the feedback path between the VCO output and the input of the PFD. Where the VCO output needs to be altered between two or more center frequencies associated with corresponding communication channels serviced by the RF transceiver, the frequency divider will have a selectable denominator “N” by which the feedback signal will be down scaled. The selection of denominators corresponds with the selection of a communication channel.
Where the center frequencies of the channels serviced by the RF transceiver are not integer multiples of the reference signal frequency the frequency divider may be a fractional divider with a selectable denominator. In these implementations a ditherer may also be added to smooth out any periodic spikes in the fractional divide by values which would otherwise result in periodic shifts of the VCO output phase by more than an entire wavelength. The ditherer may include both a frequency divider and an accumulator with the accumulator accumulating the least significant bits (LSB) of the divider's quotient and feeding them back into the numerator subsequently input to the frequency divider. A more complex ditherer may include both integer and fractional frequency dividers and a sigma-delta module rather than an accumulator to perform the dithering. The sigma-delta module typically adds a random sequence to the LSB of either the numerator or the quotient of one of the frequency dividers to shape the high frequency characteristics of the PLL.
For Fractional PLL's any non-linearity in any component is magnified by the scale factor between the low frequency reference signal and the high frequency VCO output signal frequency. The higher the scale factor, the more critical the errors induced by non-linearity become. Conventional charge pump design suffers from nonlinearity due to short switching pulses and the time constant for the sub-blocks to settle to its steady state. Charge pump linearity also suffers due to change in the source and sinks current differing as a function of input signal.
What is needed are improved circuits for improving the linearity of a charge pump.